HW Information-Flow Tracking for Pre-Silicon Security Testing (Princeton, MIT, EPFL)

Executive Briefing & Key Highlights

Researchers at Princeton University, MIT CSAIL, and EPFL published a technical paper titled “Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing.” Abstract “Register-Transfer Level (RTL) simulation is widely used to test hardware before it is fabricated. To allow testing for security related information flow properties, such as confidentiality and integrity, taint logic c