Self-Supervised Layout Generation To Fix Advanced-Node DRVs (Nvidia, Duke)

Executive Briefing & Key Highlights

Researchers from NVIDIA and Duke University published a technical paper titled “SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes.” Abstract “As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing ge