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Analog & Mixed-Signal IC Layout Engineer
Texas Instruments
FellowshipOfficial Link Verified33 days left
Deadline in 33 days
Description
Cadence Virtuoso layout implementation of precision analog power management ICs, ADC/DAC converters, and PLL clock generators. In-depth understanding of matching, latchup, and electromigration rules.
Eligibility
- B.Tech / M.Tech in Electrical / Electronics Engineering.
Quick Facts
Position Type
Fellowship
Organization Type
Private
Work Location
Bangalore, India
Compensation / Stipend
₹15,000,000 - ₹24,000,000/year
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Quick Facts
Location
Bangalore, India
Type
Fellowship
Deadline
18 Sept 2026
Stipend
₹15,000,000 - ₹24,000,000/year
Org. Type
Private
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