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Physical Design Engineer - Floorplanning & STA
AMD
FellowshipOfficial Link Verified40 days left
Deadline in 40 days
Description
Execution of 3nm silicon physical design implementation for Radeon GPU compute units. Responsible for Innovus place and route, CTS tree synthesis, IR drop analysis, and DRC/LVS clearance.
Eligibility
- M.Tech in VLSI / Microelectronics preferred.
Quick Facts
Position Type
Fellowship
Organization Type
Research
Work Location
Bangalore, India
Compensation / Stipend
₹17,000,000 - ₹26,000,000/year
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Quick Facts
Location
Bangalore, India
Type
Fellowship
Deadline
25 Sept 2026
Stipend
₹17,000,000 - ₹26,000,000/year
Org. Type
Research
AI Analysis & Insights
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