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TSMC Senior R&D Engineer - 2nm N2 Gate-All-Around
TSMC
FellowshipOfficial Link Verified75 days left
Deadline in 75 days
Description
R&D process development for TSMC 2nm (N2) & A16 process nodes. Nano-sheet device optimization, High-NA EUV optical proximity correction (OPC), and silicon yield enhancement.
Eligibility
- M.S / PhD in Semiconductor Physics / Materials Science / ECE.
Quick Facts
Position Type
Fellowship
Organization Type
Research
Work Location
Hsinchu, Taiwan
Compensation / Stipend
Competitive Global Package + Stock Grants
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Quick Facts
Location
Hsinchu, Taiwan
Type
Fellowship
Deadline
30 Oct 2026
Stipend
Competitive Global Package + Stock Grants
Org. Type
Research
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