All Opportunities
P
Physical Design
Physical Design engineers convert gate-level netlists into silicon-proven layout designs for ASICs and SoCs. They master standard-cell placement, clock tree synthesis (CTS), routing, and signoff Static Timing Analysis (STA).
Relevant Degrees: M.Tech in VLSIB.E./B.Tech in ElectronicsM.S. in EEPh.D. in VLSICommon Skills: Static Timing Analysis (PrimeTime)Place-and-Route (Innovus / ICC2)SynthesisDRC/LVS (Calibre)IR Drop & Electromigration (RedHawk)
No active positions right now
New positions are added daily. Check back soon or browse all opportunities below.