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Marvell Technology

Verified

Position available at official Marvell Technology careers portal. Requisition: N/A

Marvell Technology

Verified

Position available at official Marvell Technology careers portal. Requisition: N/A

Marvell Technology

Verified

Position available at official Marvell Technology careers portal. Requisition: N/A

Graphcore

Verified

About us Graphcore is one of the world's leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world's most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore's teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore brings together deep expertise to solve complex problems and deliver meaningful progress in AI compute. Job Summary Reporting to the Head of Data & Transformation, the Staff Data Engineer – Agentic Applications is a senior individual contributor responsible for designing, building and operating Python-based web applications, agentic workflows and supporting data services for Graphcore’s business teams. The role combines strong data engineering foundations with hands-on application development, using AI agents, trusted data and business system integrations to improve decision-making and automate operational workflows. Depending on the use case, you will either deliver applications end to end, using AI-assisted coding tools to build and maintain the front end, or own the backend and enable business colleagues to create and look after their own front ends. In both approaches, you will help establish clear ownership, secure interfaces and appropriate engineering controls so applications remain reliable, maintainable and supportable. Working closely with engineers, analysts and business stakeholders, you will take solutions from initial requirements through to production, contribute to the evolution of the underlying data platform and provide technical leadership through design reviews, code reviews and mentoring. The Team The Data & Analytics team enables better decision-making across Graphcore by building trusted data foundations, scalable platforms and high-quality data products. The team works across a broad range of business and technical domains, partnering with colleagues throughout the company to improve access to reliable information, strengthen operational insight and support efficient, data-informed ways of working. Within this team, the Staff Data Engineer – Agentic Applications turns these foundations into practical business applications and automated workflows. The role also enables colleagues outside engineering to participate in application development, supported by reusable services, clear guidance and appropriate governance. Responsibilities and Duties Build business-facing applications. Design, develop and operate production-ready Python web applications that help business teams access trusted data, complete tasks and improve operational workflows. Develop agentic capabilities. Build applications and workflows that connect AI agents to approved tools, APIs, datasets and business systems, with clear boundaries on what agents can access and do. Translate business needs into working solutions. Partner with analysts, engineers and business stakeholders to understand user needs, identify appropriate opportunities for automation and take applications from prototype through to supported production services. Deliver end-to-end applications where appropriate. Use AI-assisted coding tools to build and maintain front ends alongside Python backend services, taking responsibility for the quality, testing, security and maintainability of generated code. Enable business-owned front ends. Where business teams develop and maintain their own interfaces, own the backend and provide documented APIs, reusable templates, examples and practical coaching so colleagues can work effectively with AI-assisted coding tools. Establish clear ownership and support arrangements. Agree responsibilities for application changes, testing, releases and ongoing support, including appropriate review and deployment controls for business-maintained front ends. Build secure, reusable backend services. Design APIs and application services that enforce authentication, authorisation, input validation and business rules, keeping secrets and sensitive operations within controlled backend systems. Engineer reliable agentic workflows. Implement appropriate evaluation, monitoring, audit trails and safeguards, including constrained tool permissions, human approval for consequential actions and safe handling of failures or unreliable model outputs. Maintain strong data foundations. Design, build and enhance Python-based batch and streaming pipelines, trusted datasets and reusable data models that support applications, analytics, reporting and operational workloads. Own key platform components. Take ownership of relevant backend and data-platform services, using AWS services including S3, Lambda, Aurora PostgreSQL, Athena, Glue and Redshift to deliver secure, resilient and cost-effective solutions. Enable safe, repeatable delivery. Build and maintain orchestration, CI/CD workflows, automated testing, deployment processes, monitoring and operational support for applications and data workflows. Improve resilience and performance. Apply robust error handling, idempotent processing, retry and recovery mechanisms, and backfill or replay capabilities to improve reliability, scalability and operational performance. Apply engineering and governance standards. Contribute to standards for data quality, documentation, observability, security and access management, including least-privilege access, database permissions and secure secrets handling. Provide technical leadership. Review designs and code, mentor engineers and guide business application builders, helping raise engineering quality across both manually written and AI-generated software. Improve shared capabilities. Identify opportunities to simplify delivery, reuse application patterns and enhance platform capabilities, contributing to technical roadmaps and engineering practices across the Data & Analytics team. Candidate Profile Essential Strong experience designing, building and operating production-grade data pipelines and platforms using Python. Experience building and supporting Python web applications, backend services and APIs that integrate data and business systems. Practical experience developing applications or workflows that use large language models or AI agents, including connecting them to tools, APIs and governed data sources. Experience using AI-assisted coding tools effectively, with the ability to understand, review, test, debug and maintain generated code rather than relying on generated output without validation. Ability to either build usable web front ends with AI-assisted tools or enable business colleagues to develop and maintain front ends against well-defined backend services. Sufficient understanding of web development to review integrations and troubleshoot application behaviour is required; deep specialist front-end expertise is not essential. Strong hands-on experience with modern orchestration, automated testing, CI/CD, deployment and monitoring practices in production environments. Experience building cloud-based solutions using AWS services, including data storage, processing and query technologies. Strong understanding of data modelling, schema design, data quality and performance optimisation across relational and analytical systems. Experience working with both batch and streaming data pipelines, including operational support, troubleshooting and designing systems that recover gracefully from failures. Strong understanding of security, access control and governance for cloud-based data platforms and applications, including authentication, authorisation, IAM, database permissions and secure secrets management. Practical understanding of the reliability and security considerations of agentic applications, including permission boundaries, evaluation, auditability and appropriate human oversight. Experience providing technical leadership as a senior individual contributor through design reviews, code reviews, engineering standards and mentoring. Ability to collaborate effectively with technical and non-technical stakeholders, translate business requirements into practical, scalable solutions and explain technical concepts clearly. Ability to coach business colleagues in AI-assisted application development and establish clear boundaries between business-owned interfaces and engineering-owned services. Desirable Experience with Python web application frameworks such as Streamlit, Flask or FastAPI. Working knowledge of JavaScript or TypeScript and a modern front-end framework. Experience with agent orchestration, retrieval over business data, or automated evaluation of AI-enabled applications. Experience with Prefect or a similar workflow orchestration platform. Experience with streaming or data collection technologies. Experience with PostgreSQL, Redshift, ClickHouse or similar database and data warehouse technologies. Experience with Infrastructure as Code and reusable application deployment patterns. Familiarity with dbt and analytics engineering practices. Experience improving observability, operational monitoring, application performance and cloud cost optimisation. Experience contributing to technical roadmaps and platform improvements within a collaborative engineering team. Experience working within a fast-moving technology or engineering environment. Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications

Marvell Technology

Verified

Official opening at Marvell Technology. Role involves advanced engineering across design, testing, verification, and silicon delivery pipelines. Candidate will collaborate with multi-site engineering teams on high-performance compute and semiconductor architectures. Apply directly via official career portal.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Mid Core Design Verification Engineer to help verify the next generation of high-performance RISC-V CPU cores. You’ll work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and uncover the corner cases that matter in a modern out-of-order processor. This is a hands-on role where you’ll have the opportunity to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on verification engineer who enjoys understanding how CPUs work and finding the bugs others miss. Comfortable working across architecture, microarchitecture, RTL, and verification to understand complex CPU behavior. A strong problem solver who can debug failures, identify root causes, and work collaboratively toward solutions. Organized and self-motivated, with the ability to take ownership of verification tasks while working effectively within a larger team. Curious about high-performance processors, RISC-V, and the challenges of verifying increasingly complex CPU designs. What We Need 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs. Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage. Understanding of CPU architecture and/or microarchitecture, ideally including concepts such as pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling. Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools. Strong C/C++ or Python skills and the ability to work effectively with RTL designers, architects, and other verification engineers. What You Will Learn Gain deep hands-on experience verifying high-performance, out-of-order RISC-V CPU cores. Learn how CPU microarchitecture decisions translate into RTL and how those designs are verified against architectural intent. Develop expertise in advanced verification techniques for complex processor pipelines and interacting subsystems. Work closely with CPU architects and RTL engineers to understand the full design lifecycle from specification through silicon. Build experience with the challenges of verifying next-generation CPUs designed for AI, HPC, and high-performance computing systems. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You’ll work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch. You’ll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This is an opportunity to make a direct impact on the performance and correctness of a high performance out-of-order CPU. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs. Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch. A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes. Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers. Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance. What We Need 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs. Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development. Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution. Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools. Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams. What You Will Learn Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU. Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently. Develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes. Learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments. Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives the implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes. This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You are an experienced Physical Design Engineer with 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs. You bring deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification. You have built or owned physical design methodology, automation, or CAD flows and are highly skilled in Tcl, Python, Perl, or similar scripting languages. You are a technical leader who can influence across teams, mentor engineers, and drive standards across geographically distributed organizations. What we need Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification. Explore AI/ML-enabled PD tooling, begin synthesis and PnR of CPU partitions, and start developing the new program RM flow. Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows that improve predictability, turnaround time, and PPA. Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design. What you will learn How to apply AI/ML to physical design for hotspot prediction, congestion forecasting, timing-risk classification, ECO prioritization, IR-drop screening, and flow tuning. How to build reliable, explainable, production-ready data infrastructure, including feature collection, validation, and signoff integration. How to evaluate AI-enabled EDA capabilities and determine where data-driven optimization delivers measurable value over conventional heuristics. How to scale CPU methodology, automation, and AI/ML deployment across advanced-node programs, foundries, teams, and the broader organization. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Graphcore

Verified

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware engineers, validation engineers, and diagnostics teams to understand new hardware capabilities and translate them into reusable diagnostic software. Responsibilities Learn and extend existing Arm diagnostics tools to support Graphcore’s AI platform. Develop specialized diagnostics and stress-testing software for CPU, memory, interconnect, PCIe, and other system components. Build reusable validation utilities that integrate into the existing validation framework. Develop tools that expose intermittent hardware failures including silent data corruption, timing-related issues, and hardware instability. Design configurable diagnostic applications supporting multiple silicon revisions, platforms, and execution environments. Develop automation for executing diagnostics across server and rack-scale validation environments. Design configuration-driven diagnostics supporting scalable parameterization and workload variation. Collaborate with hardware architects to understand new hardware capabilities and identify missing diagnostics. Work closely with firmware and validation teams to improve hardware observability. Debug low-level hardware, firmware, operating system, and driver interactions. Analyze diagnostic output and improve fault isolation methodologies. Develop software that enables engineers to reproduce and investigate difficult hardware failures. Contribute reusable libraries and utilities that improve engineering productivity across multiple validation teams. Candidate Profile Essential Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical discipline. 10+ years of experience developing hardware diagnostics, system validation software, firmware validation tools, or low-level systems software. Strong software development skills in Python and C/C++. Strong Linux systems experience. Strong understanding of modern server platform architecture, including how CPU, memory, PCIe, storage, networking, firmware, operating system, and device drivers interact within a complete system. Experience debugging hardware/software interactions across multiple layers of the platform. Experience developing diagnostics, stress testing, or hardware validation software. Experience with server platforms, embedded systems, or SoC validation. Strong analytical and debugging skills. Experience collaborating across hardware, firmware, software, and validation teams. Excellent communication and problem-solving skills. Desirable: Preferred Qualifications Arm-based server platforms AI accelerators or high-performance computing systems Silent Data Corruption (SDC) testing Hardware stress testing Power transient analysis Hardware fault injection methodologies Firmware validation Silicon bring-up Performance characterization Hardware telemetry and observability BMC firmware or server management RAS (Reliability, Availability, Serviceability) technologies Validate across subsystems: CPU scaling and cache behavior Memory (DDR/HBM) bandwidth, latency, and NUMA effects Interconnect contention under multi-core load PCIe/I-O throughput, latency, and multi-device scenarios High-speed I/O validation What Success Looks Like Successful candidates will: Extend existing diagnostics technologies to support new Graphcore hardware. Develop new diagnostics tools for emerging hardware capabilities. Build reusable software components that integrate seamlessly with the existing validation framework. Improve hardware observability and root-cause isolation. Detect and characterize intermittent hardware failures that traditional validation techniques cannot expose. Deliver configurable diagnostics that scale across multiple platforms and silicon revisions. Work effectively across hardware, firmware, validation, and diagnostics teams to continuously improve platform quality. Why Join Graphcore? This role provides a unique opportunity to work at the intersection of hardware architecture, diagnostics, and software engineering while helping define how next-generation AI systems are validated. Rather than maintaining an existing validation framework, you will develop the specialized diagnostics and stress tools that make that framework valuable. Your work will directly influence hardware quality, silicon bring-up, and long-term platform reliability for future AI infrastructure. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to the Director of Automation, the Staff Robotics Engineer will provide technical leadership for the design, integration, validation, and deployment of robotic automation systems for data center operations. This role will work closely with internal Graphcore teams, SoftBank Robotics, SoftBank Group affiliates, and external technology partners to turn R&D concepts into scalable, production-ready robotic capabilities. Example systems may include robotic manipulation, material transport, inspection, rack/server handling, autonomous mobile robots, or other automation solutions for data center operations. This role is based in Austin and may require periodic travel to partner, manufacturing, lab, or deployment sites, including occasional collaboration across APAC time zones. The Team The automation team is responsible for helping the vision of Softbank Group to automate data center, working with internal Graphcore teams and Softbank Group affiliates. The team works closely with Softbank Robotics and its partners and other third parties to solve complex solutions for data center operations. Our focus is on delivering robust, production-quality systems that bridge cutting-edge research and real-world deployment. Responsibilities and Duties This role is expected to operate with high autonomy, define technical direction for ambiguous robotics automation problems, influence partner roadmaps, and establish engineering standards for scalable deployment. Align robotics, data center, internal engineering, SoftBank Group, and third-party partner teams to provide scalable autonomy capabilities. Guide and mentor Softbank Group engineers and third-party partners without direct people management responsibilities, elevating technical judgment and Mechatronics best practices. Contribute to technical planning, estimation and delivery of key project milestones. Experience establishing or executing verification and validation processes, including simulation, hardware-in-the-loop testing, FAT/SAT, site validation, or field deployment. Support troubleshooting and root-cause analysis across software, controls, mechanical, and electrical systems. Iterate on end effectors, hardware interfaces, and robotic subsystems with partners. Help build scalable software infrastructure, device management systems, and fleet coordination protocols by collaborating with Softbank Group affiliates and third-party partners. Lead the transition of R&D feasibility studies into production-ready integrated systems. Evaluate emerging technologies, tools and methodologies to improve robotics capabilities and engineering productivity. Produce clear technical documentation and communicate engineering decisions effectively to a range of stakeholders. Candidate Profile Essential 8+ years of experience in automation or equipment engineering, with a focus on mechatronic subsystems and modular machine design. Experience taking robotic or automated systems from prototype/R&D into production or field deployment. Experience with material handling systems, automated equipment, or productionized robotic solutions. Familiarity with 3D localization or VLM-based object detection (e.g., perception/ segmentation). Experience conducting FAT/SAT validation and managing technical deliverables with partners and manufacturers. Proven ability to debug the "full-stack": PLC logic, high-level code (C# or Python), and complex mechanical/electrical hardware. Experience with robotics frameworks and middleware such as ROS/ROS 2 and IsaacSIM for modeling robotic interactions and path planning. Strong understanding of robotics fundamentals including perception, localization, mapping, planning or control. Ability to lead technical initiatives and influence engineering direction through expertise and collaboration. Excellent problem-solving and analytical skills. Strong communication skills with the ability to work effectively across multidisciplinary teams. Degree in Mechatronics, Mechanical Engineering, Electrical Engineering, Computer Science, Robotics, Mathematics, or a related technical field, or equivalent practical experience. Desirable Experience applying machine learning or AI techniques within robotics systems. Experience with simulation environments and digital twin technologies. Knowledge of computer vision, sensor fusion or reinforcement learning techniques. Experience deploying robotics applications to cloud, edge or embedded environments. Familiarity with GPU acceleration, high-performance computing or AI infrastructure. Experience contributing to open-source robotics projects or technical communities. Experience working in research-intensive or advanced technology environments. Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 10 years experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 8 years of strong experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment. Responsibilities and Duties Lead advanced break-fix troubleshooting for server blades, motherboards, power systems, and rack-scale infrastructure. Support engineering bring-up activities, including component validation and firmware interaction testing. Diagnose system-level failures involving thermal behavior, power anomalies, network configuration, and BIOS/BMC issues. Collaborate with server engineering teams to perform root cause analysis and propose corrective actions or design improvements. Support deployment and rollout of next-generation hardware platforms through structured validation and qualification cycles. Interface with facilities and infrastructure teams to understand environmental factors impacting system reliability. Develop and maintain standard operating procedures (SOPs), troubleshooting guides, and validation documentation. Provide guidance and mentorship to junior technicians and engineers on troubleshooting methodologies and hardware diagnostics. Participate in on-call rotations or off-hours support during critical engineering milestones or hardware bring-up phases. Candidate Profile Essential Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. 7 years experience with server hardware architectures and board-level debugging. Experience analyzing system logs, hardware telemetry, and power/thermal metrics to isolate hardware failures. Hands-on experience with HPC systems, AI compute platforms, or rack-scale infrastructure. Strong collaboration skills and ability to work effectively in fast-paced engineering environments. Excellent written and verbal communication skills. Desirable Experience supporting prototype or pre-production hardware bring-up. Familiarity with data center facilities, including liquid cooling and power distribution systems. Experience using Python, Bash, or automation tools for hardware validation or troubleshooting. Exposure to structured failure analysis and reliability engineering methodologies. USA Benefits In addition to a competitive salary, Graphcore offers flexible working and a comprehensive benefits package designed to support your health, wellbeing and financial future. Our benefits include medical, dental and vision coverage, Flexible Spending Accounts (FSAs), Health Savings Accounts (HSAs), disability and life insurance, a 401(k) retirement plan, commuter benefits, wellness services and an Employee Assistance Programme (EAP). We welcome people of different backgrounds and experiences; we're committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Join our dynamic Software Infrastructure team and take a pivotal role in scaling and managing our infrastructure. You will develop essential tools and services that empower our broader software team. Your contributions will enhance the build, test, deployment, and productisation processes of our Machine Learning Software components. Work with our High-Performance Computing (HPC) AI platforms and gain invaluable experience in distributed systems. The Team An exciting opportunity to join a new team within the Software Operations group. The Build Engineering team is a new function within Software Infrastructure, which focuses on the overall process of building and integration of the Machine Learning Software Stack. You will work closely with the QA and development teams to get an understanding of how our ML SW stack is built, helping to ensure good build practices, and proving that the stack works together and is reproducible in secure, sandboxed environments. Responsibilities and Duties Developing our internal tooling for building, testing and integrating together the ML Software Stack Developing tools and technical processes for Software Releases Providing guidance to developers on best build practices and dependency management Communicating regularly with developers, tech leads, and software architects about aspects of the ML Software Stack Working closely with QA and the ML Software Stack to resolve any integration issues Contributing fixes towards the ML Software Stack Essential: Knowledge of Python/C++ (or similar language) Understanding of Build Processes and Frameworks Experience working in Linux environments Good communication skills Desirable: Experience with Remote Caching and Execution (e.g. Bazel) Experience with Build Tools (e.g. CMake) Experience with Testing Frameworks (e.g. PyTest, GoogleTest) Experience with Integration Tools (e.g. Buildstream) Experience working within the Software Development Lifecycle (SDLC) Experience with building and using containers (e.g. Docker, Podman) An understanding of Software Architecture patterns Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications

Back to jobsField Application Engineer, South East AsiaSingaporeApplyTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.We are looking for a Field Application Engineer to serve as the technical bridge between Tenstorrent and customers across Southeast Asia. Based in Singapore, you will work closely with customers, partners, sales, and global engineering teams to understand AI and machine learning workloads, guide technical evaluations and deployments, troubleshoot issues across hardware and software, and help customers realize the performance of Tenstorrent’s AI platforms. This is a highly visible, customer-facing role that combines hands-on technical problem solving, solution development, and regional relationship building, with regular travel throughout Southeast Asia. This role is remote, based out of Singapore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A customer-focused technical professional who can build trust with application developers, engineering teams, and business stakeholders. Comfortable translating complex AI/ML hardware and software concepts into clear recommendations for both technical and non-technical audiences. A proactive and self-directed problem solver who can coordinate internal teams, external service providers, and customer stakeholders across South East Asia. Willing and able to travel to customer sites for installations, maintenance, troubleshooting, demonstrations, and proof-of-concept delivery. What We Need Experience as a Field Application Engineer, Application Engineer, Sales Engineer, Solutions Architect, or in a similar customer-facing technical role focused on AI/ML software and hardware. Strong Python programming skills and deep familiarity with AI/ML frameworks such as PyTorch and TensorFlow; experience with Generative AI, LLMs, vision models, model deployment, training, or fine-tuning is preferred. Experience designing scalable AI solutions and deploying applications in cloud environments, as well as physically installing, moving, and repairing servers, accelerator cards, and PCIe devices. A Bachelor's degree or higher in Computer Science, Engineering, or a related field. Experience with C++, CUDA, parallel programming, or kernel develo

Back to jobsEmulation EngineerTokyo, JapanApplyTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.We are looking for an Emulation Engineer to develop and deploy emulation solutions for complex SoC and chiplet-based designs. In this role, you will work closely with RTL, DV, architecture, firmware, and software teams to enable early software bring-up, improve verification throughput, and accelerate debug on emulation platforms. This role is ideal for someone who enjoys solving system-level problems, improving validation efficiency, and building scalable emulation infrastructure that can be reused across projects. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with solid experience in SoC or chiplet-based emulation, prototyping, or verification. You are fluent in SystemVerilog and comfortable working across DPI-C, C or C++, Python, and shell scripting for automation, debug, and test enablement. You have hands-on experience with commercial emulation platforms such as Cadence Palladium, Synopsys ZeBu, Siemens Veloce, or HAPS, and understand how to adapt environments for functionality, performance, and scalability. You are a collaborative and self-driven engineer who works effectively across RTL, DV, firmware, and architecture teams and is comfortable debugging issues across hardware and software boundaries. What We Need Develop and maintain emulation environments for block, subsystem, and full-chip or chiplet systems, including porting simulation test benches and workloads onto hardware-assisted verification platforms. Optimize test benches, transactors, trackers, and checkers for emulation readiness, performance, scalability, and regression throughput. Drive early use-case verification and software bring-up by integrating boot flows, firmware, bare-metal tests, OS bring-up, and system-level workloads into the emulation environment. Debug failures across RTL, test bench, firmware, and emulation infrastructure while creating reusable collateral, scripts, and methodology improvements that help internal teams use emulation more e

Graphcore

Verified

Silicon Verification Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The verification team sits within the Silicon design team and is responsible for ensuring that the RTL created by the logical design team and used by the physical design team matches the architecture specification for Graphcore silicon. The silicon verification engineer is responsible for verification activities within Graphcore, helping the team meet the company objectives for quality silicon delivery. Responsibilities Verification planning, specification and closure of functional coverage Providing feedback to architects Test generation and failure diagnosis/triage Contributing to shared verification infrastructure Ensuring good communication between sites Essential skills: • Verification experience in relevant industry • Proven leadership and planning skills • Highly motivated, a self starter, and a team player • Ability to work across teams and programming languages to find root causes of deep and complex issues • Experience of the verification process applied in CPU and/or ASIC environments • System Verilog, Python, C++, Linux Desirable skills: • UVM • SVA • Assembly languages • LLVM, GCC • DVCS e.g. Git • SGE or other DRMS • XML and XPath/XSLT • Web programming – HTML/DOM, Javascript, SQL Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

Salary Range: PLN 350,700 - 474,400 PLN Subject to alignment to the responsibilities and duties of the role About the job Help Graphcore’s Frameworks engineers in Gdańsk build the tools that make our hardware easier to use. Reporting to the Director of Frameworks, you will lead engineers contributing to our PyTorch and Triton teams. You will support their development, clarify priorities and keep feedback flowing across locations. This role blends people leadership with real technical ownership. You will contribute to PyTorch, Triton or related Frameworks work through design, implementation, review, debugging, testing or performance analysis. You will help engineers deliver high-quality work while staying fully connected to their teams. It is a rare chance to shape both software outcomes and engineering culture at a growing site. The team and culture Frameworks makes Graphcore hardware work seamlessly with the tools machine learning engineers and researchers use. The team builds PyTorch support, an out-of-tree Triton backend, framework integrations, runtime components, kernels, tests, performance tooling and user documentation. Work happens across locations, so clear writing, shared context and constructive challenge matter. You will help Gdańsk engineers stay close to technical leaders, team priorities and the decisions shaping delivery. People are trusted to take responsibility, speak up and move with purpose. The team values learning, maintainability, performance, ease of use and thoughtful collaboration with open-source communities. What we’re looking for Experience managing and developing software engineers, including coaching, feedback, performance management and career development Strong software engineering capability, with professional experience in C++ and Python Clear written and verbal communication in English and Polish, especially when explaining complex technical context Ability to build alignment across teams, locations and disciplines Pragmatism when balancing people leadership, hands-on technical contribution, engineering quality and delivery Experience with PyTorch, Triton, compiler development, MLIR, LLVM, machine learning kernels or accelerator architectures While we have outlined a set of requirements, we value transferable skills and diverse experiences. We also welcome engineers returning to the profession after a career break, including through returnship routes. Benefits Flexible working: Balance your work and personal life with greater flexibility Comprehensive healthcare and dental cover: Premium medical and dental insurance, with the option to extend cover to your family Phantom equity: Share in Graphcore’s success Fitness and wellbeing support: A fully funded Medicover gym card, giving you access to a wide range of gyms, fitness classes and leisure centres Financial protection: Death and disability insurance, providing financial security for you and your loved ones Retirement savings: Build your financial future, with a 4% employer contribution from Graphcore, alongside your own contributions Employee Assistance Programme (EAP): Confidential advice and support for you and your family across a range of personal, financial and wellbeing matters We welcome people from all backgrounds and experiences and are committed to building an inclusive environment where everyone can do their best work. We’re an equal opportunity employer and recognise that everyone brings different strengths and perspectives. If you need any adjustments during the interview process, just let us know - we’re happy to support you. Sponsorship Applicants must have the legal right to work in Poland. Unfortunately, we are unable to provide visa sponsorship or support visa applications for this role. Join the Team at Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore brings together deep expertise to solve complex problems and deliver meaningful progress in AI compute. If you want to lead engineers while staying close to the technology that powers AI frameworks, we’d love to hear from you. Apply now to help shape Frameworks at Graphcore.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration. Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs. Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations. A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments. A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors. Strong communication skills and the ability to mentor and guide engineering teams. What We Need Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs. Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals. Drive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements. Bring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification. What You Will Learn Work on cutting-edge CPU and AI compute architectures integrating advanced compute, memory, and interconnect technologies. Gain exposure to large-scale system integration challenges spanning RTL, verification, physical design, and silicon bring-up. Influence key architectural and microarchitectural decisions that directly impact next-generation product performance and scalability. Collaborate with highly experienced global engineering teams across multiple domains and disciplines. Contribute to the evolution of scalable IP integration methodologies, verification flows, and best practices for future SoC programs. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in close collaboration with design and architecture teams. What You Will Learn Build deep expertise in system management and multi-die SoC verification. Gain hands-on exposure to advanced interconnect standards like UCIe and BoW. Explore co-simulation methodologies including Cocotb. Learn how AI tools can accelerate test generation, infrastructure, and debug workflows. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node methodology, low-power intent (UPF/CPF), clock tree synthesis, and signoff (EM/IR, DRC/LVS). Experience standing up flows for new technology nodes, PDKs, or foundry targets ahead of program need, and qualifying new EDA releases. What You Will Learn How to build and scale EDA automation for AI accelerators and high-performance CPUs on advanced FinFET/GAA nodes. ML-driven flow optimization and custom CAD development at production scale. How to influence EDA vendor roadmaps through direct technical partnership. How multi-variant, multi-foundry IP delivery works, and how flow readiness moves customer commit dates. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes. Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets. Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout. Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)). Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports). What You Will Learn How RISC-V CPU and AI accelerator IP is hardened and delivered to external licensees on the most advanced process nodes. Multi-variant IP delivery: porting the same block across nodes, foundries, and PPA targets. Direct impact on IP deal timelines, since your PPA and schedule data feeds our customer commitments. Front-to-back co-design with architecture, RTL, and chiplet integration teams. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation CPU and AI silicon. You’ll work at the forefront of hardware innovation, diagnosing complex issues across chips, systems, firmware, and software while collaborating with some of the brightest engineers in the industry. This role offers the opportunity to solve challenging technical problems, build impactful debug solutions, and directly influence the reliability and performance of cutting-edge AI compute platforms. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in hardware debug and post-silicon bring-up for CPU, SoC, or ASIC systems. Strong understanding of processor architecture and microarchitecture (RISC-V, x86, or ARM) with familiarity in debug and trace methodologies (e.g., iJTAG). Hands-on engineer who excels at diagnosing complex hardware, firmware, and software issues through root-cause analysis. Comfortable working in the lab with a passion for building debug tools, automation, and scalable methodologies. Collaborative team player with experience partnering across ASIC, firmware, software, and validation teams. What We Need Lead post-silicon debug across Tenstorrent's AI accelerator platforms, diagnosing hardware and firmware issues on silicon, boards, and systems. Debug complex issues spanning power, thermal, GDDR, PCIe, Ethernet/SerDes, NoC, and firmware (including metal and Ethernet). Develop Python and C-based diagnostic tools, automation, and debug frameworks to accelerate failure analysis. Utilize lab equipment such as oscilloscopes, logic analyzers, and protocol analyzers to investigate system-level failures. Analyze schematics, register states, telemetry, and firmware behavior to identify root causes and drive resolution. What You Will Learn Gain hands-on experience bringing next-generation AI accelerator silicon from prototype through production. Develop expertise across the full hardware stack, including silicon, boards, firmware, drivers, and system software. Collaborate with world-class ASIC, firmware, and software engineers to solve complex AI hardware challenges. Deepen your knowledge of high-speed interfaces, including GDDR/DDR, PCIe, Ethernet/SerDes, power management, and system validation. Help build scalable debug infrastructure and methodologies that improve the reliability and performance of Tenstorrent's AI platforms. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on Staff Software Engineer with a platform infrastructure / Site Reliability Engineering (SRE) background to help build and operate the systems behind Tenstorrent’s AI cloud. This team develops and runs both on-prem and public cloud infrastructure and services that support high-performance AI workloads. The role spans backend development, service integrations, infrastructure-as-code, CI/CD, and reliability engineering, with room to go deeper in a specialty while working across the stack. This role is hybrid, based out of Austin, TX; Santa Clara, CA; or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong software engineer with a track record of designing and delivering complex production services and applications. Fluent in Python, with Go and/or TypeScript as a plus. Experienced with Kubernetes and comfortable working across bare metal, virtual machines, and modern cloud infrastructure; AWS experience is a plus. Familiar with observability and production operations across hardware, system, and application layers, including monitoring, alerting, and telemetry. Bonus points for depth in network automation, storage platforms, and/or cloud or application security. What We Need Build and improve backend services and platform integrations that power Tenstorrent’s on-prem and public AI cloud environments. Raise the bar on infrastructure automation through CI/CD and Infrastructure-as-Code practices using tools such as Ansible and Terraform. Strengthen platform reliability with better observability, monitoring, alerting, and operational response across the stack. Partner effectively with end-users, peers, and domain experts to turn complex infrastructure needs into dependable systems. Bring technical leadership, strong engineering judgment, and a mindset of continuous learning that helps the team scale its capabilities. What You Will Learn How AI cloud infrastructure comes together end-to-end, from data center hardware and fleet operations to user-facing services and interfaces. What it takes to run reliable, high-performance AI workloads across both on-prem and public cloud environments. How hardware, software, networking, storage, and operations intersect inside a real-world AI platform. How to expand into adjacent parts of the stack without getting boxed into a narrow silo. How to apply the latest AI tools in day-to-day engineering work while building practical systems that matter. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-standard tools (Innovus, PrimeTime, RedHawk) and scripting languages (Tcl, Perl, Python). Deep understanding of advanced node challenges and low-power design techniques (power gating, multi-Vt, voltage scaling). Experience driving physical design requirements from early architecture through final signoff. What You Will Learn How to implement cutting-edge AI accelerators and high-performance CPUs on the most advanced process nodes. Innovative PPA optimization techniques and methodologies for next-generation chiplet architectures. End-to-end ownership from flow development to signoff in collaboration with architecture and IP teams. Direct impact on products that are redefining the landscape of AI and high-performance computing. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade. This role is hybrid, based out of Toronto, ON, Austin, TX or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development. Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms. Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines. Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios. Motivated by AI hardware and eager to learn verification strategies for new architectures and domains. What We Need Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning coverage goals and driving them to closure. Build and maintain reusable verification environments, agents, scoreboards, and supporting infrastructure in SystemVerilog and Python. Develop constrained-random and directed tests and close functional, code, and assertion coverage using data-driven approaches. Debug complex issues across RTL and testbench while collaborating with design, firmware, compiler, and architecture teams. Help evolve DV infrastructure including regression flows, CI/CD integration, EDA compute environments, and reproducible setups. Nice to have: Exposure to functional safety (FuSa) verification concepts for automotive AI workloads. Nice to have: Familiarity with formal verification methodologies, SVA (SystemVerilog Assertions), or formal property verification for complex control logic and microarchitectural corner cases. What You Will Learn How Tenstorrent verifies AI-native compute architectures including Tensix cores, RISC-V CPUs, matrix units, vector units, and datapath. How simulation, emulation, and software-driven workloads combine to validate both functional correctness and performance. How numerical precision formats such as BF16, FP4, and INT8 and on-chip dataflow impact verification complexity and coverage strategy. How to build scalable DV infrastructure across hybrid compute environments including containerized regression systems. How data analytics and modern AI tooling can enhance verification workflows and accelerate convergence. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join Tenstorrent and help bring next-generation AI accelerator technology from silicon bring-up to production. You’ll work at the forefront of hardware innovation, diagnosing complex issues across chips, systems, firmware, and software while collaborating with some of the brightest engineers in the industry. This role offers the opportunity to solve challenging technical problems, build impactful debug solutions, and directly influence the reliability and performance of cutting-edge AI compute platforms. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on hardware debug engineer who thrives on solving complex, cross-functional problems at the intersection of silicon, firmware, and software. A curious and analytical problem solver who enjoys digging into failures, identifying root causes, and driving issues from initial discovery through resolution. An engineer with strong post-silicon validation and bring-up experience who is comfortable working in the lab and getting deep into system-level behavior. Someone who enjoys building tools, improving debug methodologies, and creating scalable solutions that help teams move faster. A collaborative teammate who can partner effectively with ASIC design, firmware, software, and validation teams to deliver reliable AI accelerator products. What We Need A skilled Post-Silicon Debug Engineer to diagnose, root-cause, and resolve hardware and firmware issues across Tenstorrent’s AI accelerator platforms, including Blackhole, Wormhole, Galaxy systems, and PCIe cards. An engineer who can lead silicon, board, and system-level debug efforts by analyzing failures across power delivery, thermal behavior, GDDR memory, Ethernet/SerDes links, PCIe, and NoC interconnects. Strong programming skills in Python and C to develop debug scripts, diagnostic tools, and automation frameworks that accelerate failure analysis and triage. Hands-on lab expertise with tools such as oscilloscopes, logic analyzers, protocol analyzers, and other hardware debug equipment. A technical leader who can interpret schematics, datasheets, register states, telemetry data, and firmware behavior to uncover complex system issues and drive solutions. What You Will Learn Gain deep exposure to cutting-edge AI accelerator architectures and the challenges of bringing advanced silicon from prototype through production. Develop expertise across the full hardware stack, from silicon behavior and board-level design to firmware, drivers, and system software interactions. Work alongside world-class ASIC, firmware, and software engineers to solve some of the most challenging hardware and system-level problems in AI computing. Expand your knowledge of high-speed interfaces, including GDDR/DDR memory, PCIe, Ethernet/SerDes, power management, and system validation. Build and improve debug infrastructure, methodologies, and processes that directly impact the reliability and scalability of Tenstorrent products. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V-based CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Great at identifying problems and developing solutions. Enjoys building tools and optimizing work flows. Skilled in C++ and Python, with an understanding of industry-standard tools for compilation, simulation and emulation. Proficient in debugging RTL/logic across multiple design hierarchies and pre-silicon environments. Knowledgeable in architecture and microarchitecture of high-performance CPU cores. Ideal candidates would possess experience in infrastructure, methodology and performance verification. What We Need Join a team driving improvements in CPU microarchitecture, verify performance and correlate with the RTL. Enhance design environment, tools, and methodologies to improve development efficiency. Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features. Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results. What You Will Learn End-to-end exposure to CPU design from microarchitecture through performance convergence and validation. Hands-on experience optimizing CPU designs in both pre-silicon and post-silicon phases. Integration of open-source and industry-standard tools to improve flows and results. Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. About Tenstorrent Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. This role sits at the intersection of technical expertise and customer engagement, focused on helping customers and internal teams bring up and optimize AI models on Tenstorrent platforms. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Tenstorrentについて Tenstorrentは、最先端のAI技術で業界をリードし、性能、使いやすさ、コスト効率の常識を変えています。AIによってコンピューティングのあり方が再定義される中、ソフトウェアモデル、コンパイラ、プラットフォーム、ネットワーキング、半導体における技術革新を一体として進化させることが求められています。Tenstorrentの多様な技術者チームは、高性能なRISC-V CPUをゼロから開発してきました。そして、AIへの情熱と、最高のAIプラットフォームをつくりたいという強い思いを共有しています。私たちは、コラボレーション、好奇心、そして難しい課題に真摯に向き合う姿勢を大切にしています。現在、さまざまなレベルの方を歓迎しながらチームを拡大しています。 このポジションは、技術的な専門性と顧客・社内連携の両方が求められる役割であり、顧客や社内チームがTenstorrentプラットフォーム上でAIモデルを立ち上げ・最適化できるよう支援することにフォーカスしています。 本ポジションは日本・東京を拠点としたハイブリッド勤務です。 本ポジションでは、さまざまな経験レベルの候補者を歓迎しています。面接プロセスを通じて適切なレベルを判断し、オファー内容はそのレベルに応じて決定されるため、本求人票上のレベル表記と異なる場合があります. About the Role As a Software Engineer on the AI Models / System Bring-Up team, you will be responsible for porting, validating, and optimizing AI models on Tenstorrent platforms. Working across models, runtime software, and hardware, you will help connect new models, models not yet running on Tenstorrent hardware, and research-stage workloads to stable, high-performance systems. 募集ポジションについて AI Models / System Bring-UpチームのSoftware Engineerとして、Tenstorrentのプラットフォーム上でAIモデルの移植、検証、最適化を担当していただきます。モデル、ランタイムソフトウェア、ハードウェアを横断して、新たなモデルや、まだTenstorrentのハードで動作していないモデル、研究段階のワークロードを安定した高性能システムへとつなげていくポジションです Who You Are You have hands-on experience with deep learning models in at least one major framework such as PyTorch, TensorFlow, or JAX. You are strong in Python or C++, with a solid understanding of neural network architectures, training, and inference fundamentals. You are comfortable developing in Linux environments and can debug issues across software, runtime, and hardware layers. You are collaborative and curious, and hold a degree in Computer Science, Engineering, Applied Mathematics, or a related field, or have equivalent practical experience. You have business-level Japanese and sufficient English proficiency to work effectively in a global environment. 求める人物像 PyTorch、TensorFlow、JAXなど、主要な深層学習フレームワークのいずれかでのモデル実務経験をお持ちの方 PythonやC++に強みがあり、ニューラルネットワークの構造、学習、推論の基本理解がある方 Linux環境での開発に慣れており、ソフトウェア・ランタイム・ハードウェアをまたぐ課題のデバッグができる方 協調性と好奇心があり、Computer Science、Engineering、Applied Mathematics関連の学位、または同等の実務経験をお持ちの方 ビジネスレベル日本語と業務遂行が可能なレベルの英語力がある方 What We Need Port, optimize, and validate AI models such as LLMs, CNNs, recommendation models, and vision models on Tenstorrent hardware. Port and integrate models into Tenstorrent toolchains and runtime environments. Design and run experiments to evaluate model accuracy, performance, and stability. Debug cross-stack issues and collaborate closely with hardware, compiler, and runtime teams. お任せする業務 LLM、CNN、推薦モデル、ビジョンモデルなどのAIモデルをTenstorrentのハードウェアに移植、最適化したり、検証すること モデルをTenstorrentのツールチェーンおよびランタイム環境へ移植・統合すること モデルの精度、性能、安定性を評価するための実験を設計・実施すること スタック横断の課題をデバッグし、ハードウェア、コンパイラ、ランタイムの各チームと密に連携すること What You Will Learn How AI models are brought up and optimized on Tenstorrent AI accelerators. How hardware, compiler, runtime, and model teams work together to build production-ready systems. Best practices for model porting, optimization, automation, regression testing, and performance tuning. How to translate real-world model requirements into practical technical solutions. このポジションで得られること TenstorrentのAIアクセラレータ上でAIモデルをどのように動かし、最適化していくか ハードウェア、コンパイラ、ランタイム、モデルの各チームがどのように連携して実運用向けシステムを作るか モデルの移植、最適化、自動化、回帰テスト、性能チューニングのベストプラクティス 実際のモデル要件を、実用的なソリューションへ落とし込む方法 Nice to Have Experience with LLM or foundation model inference, including KV-cache optimization and quantization. Background in compiler or runtime engineering for ML workloads. Exposure to post-silicon validation, board bring-up, firmware development, or accelerator platforms. Experience working directly with customers or field teams on AI workload deployment and debugging. Strong spoken English for technical discussions with global hardware, compiler, runtime, and model teams. 歓迎要件 LLMまたは基盤モデル推論の経験（KV-cache最適化、量子化を含む） MLワークロード向けのコンパイラまたはランタイム開発の経験 ポストシリコン検証、ボードbring-up、ファームウェア開発、アクセラレータ基盤に関する経験 AIワークロードの導入やデバッグで、顧客やフィールドチームと直接連携した経験 本社とのハードウェラ、コンパイラ、ラインタイム、モデルの各チームと連携し、議論できる英会話力 This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.