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Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Mid Core Design Verification Engineer to help verify the next generation of high-performance RISC-V CPU cores. You’ll work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and uncover the corner cases that matter in a modern out-of-order processor. This is a hands-on role where you’ll have the opportunity to own meaningful portions of the verification effort—from developing test plans and architecting test benches to debugging failures and driving issues to closure. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on verification engineer who enjoys understanding how CPUs work and finding the bugs others miss. Comfortable working across architecture, microarchitecture, RTL, and verification to understand complex CPU behavior. A strong problem solver who can debug failures, identify root causes, and work collaboratively toward solutions. Organized and self-motivated, with the ability to take ownership of verification tasks while working effectively within a larger team. Curious about high-performance processors, RISC-V, and the challenges of verifying increasingly complex CPU designs. What We Need 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs. Strong experience with SystemVerilog and UVM, including testbench development, constrained-random testing, assertions, and functional coverage. Understanding of CPU architecture and/or microarchitecture, ideally including concepts such as pipelines, out-of-order execution, caches, load/store, branch prediction, or instruction scheduling. Experience debugging RTL and simulation failures using waveforms and common simulation/debug tools. Strong C/C++ or Python skills and the ability to work effectively with RTL designers, architects, and other verification engineers. What You Will Learn Gain deep hands-on experience verifying high-performance, out-of-order RISC-V CPU cores. Learn how CPU microarchitecture decisions translate into RTL and how those designs are verified against architectural intent. Develop expertise in advanced verification techniques for complex processor pipelines and interacting subsystems. Work closely with CPU architects and RTL engineers to understand the full design lifecycle from specification through silicon. Build experience with the challenges of verifying next-generation CPUs designed for AI, HPC, and high-performance computing systems. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You’ll work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch. You’ll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This is an opportunity to make a direct impact on the performance and correctness of a high performance out-of-order CPU. This role is remote, based out of North America or Spain. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs. Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch. A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes. Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers. Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance. What We Need 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs. Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development. Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution. Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools. Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams. What You Will Learn Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU. Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently. Develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes. Learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments. Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Back to jobsEmulation EngineerTokyo, JapanApplyTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.We are looking for an Emulation Engineer to develop and deploy emulation solutions for complex SoC and chiplet-based designs. In this role, you will work closely with RTL, DV, architecture, firmware, and software teams to enable early software bring-up, improve verification throughput, and accelerate debug on emulation platforms. This role is ideal for someone who enjoys solving system-level problems, improving validation efficiency, and building scalable emulation infrastructure that can be reused across projects. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with solid experience in SoC or chiplet-based emulation, prototyping, or verification. You are fluent in SystemVerilog and comfortable working across DPI-C, C or C++, Python, and shell scripting for automation, debug, and test enablement. You have hands-on experience with commercial emulation platforms such as Cadence Palladium, Synopsys ZeBu, Siemens Veloce, or HAPS, and understand how to adapt environments for functionality, performance, and scalability. You are a collaborative and self-driven engineer who works effectively across RTL, DV, firmware, and architecture teams and is comfortable debugging issues across hardware and software boundaries. What We Need Develop and maintain emulation environments for block, subsystem, and full-chip or chiplet systems, including porting simulation test benches and workloads onto hardware-assisted verification platforms. Optimize test benches, transactors, trackers, and checkers for emulation readiness, performance, scalability, and regression throughput. Drive early use-case verification and software bring-up by integrating boot flows, firmware, bare-metal tests, OS bring-up, and system-level workloads into the emulation environment. Debug failures across RTL, test bench, firmware, and emulation infrastructure while creating reusable collateral, scripts, and methodology improvements that help internal teams use emulation more e

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking an experienced and motivated System IP RTL Design Lead to drive the definition and implementation of complex datacenter class IP for our next-generation semiconductor products. The ideal candidate possesses a deep understanding of System IP and SoC architecture, IP integration challenges, and is adept at leading a design team to deliver high-quality, scalable IP solutions. This role requires strong hands-on technical leadership, excellent communication skills, and a proven track record in the successful delivery of silicon IP. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration. Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs. Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations. A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments. A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors. Strong communication skills and the ability to mentor and guide engineering teams. What We Need Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs. Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals. Drive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements. Bring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification. What You Will Learn Work on cutting-edge CPU and AI compute architectures integrating advanced compute, memory, and interconnect technologies. Gain exposure to large-scale system integration challenges spanning RTL, verification, physical design, and silicon bring-up. Influence key architectural and microarchitectural decisions that directly impact next-generation product performance and scalability. Collaborate with highly experienced global engineering teams across multiple domains and disciplines. Contribute to the evolution of scalable IP integration methodologies, verification flows, and best practices for future SoC programs. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verification: Work within the front-end DV team to build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks. Stimulus Generation: Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions. C++ Integration: Help develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking. Execution & Closure: Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified. What You Will Learn RISC-V Front-End Microarchitecture: Practical experience with high-performance RISC-V fetch pipelines and prediction structures. Maintainable DV Infrastructure: Strategies for writing unit testbenches that remain manageable as designs evolve. Tooling & Workflows: Experience using both industry-standard simulators and open-source flows (e.g., Verilator) across simulation and emulation environments. Cross-Team Collaboration: Working directly with RTL, performance modeling, and software teams to deliver reliable hardware. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. You’ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems. This role is hybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills. Experienced in writing test plans, building infrastructure, and debugging hardware/software flows. Comfortable working with remote mentorship and distributed teams. Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification. What We Need Develop and maintain SMC tests and supporting DV infrastructure. Write, execute, and track test plans for chiplet and multi-chip SoC designs. Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT. Triage, analyze, and debug issues in close collaboration with design and architecture teams. What You Will Learn Build deep expertise in system management and multi-die SoC verification. Gain hands-on exposure to advanced interconnect standards like UCIe and BoW. Explore co-simulation methodologies including Cocotb. Learn how AI tools can accelerate test generation, infrastructure, and debug workflows. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our Tensix team is building custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI. Design Verification Engineers on this team validate compute IP and subsystems and build scalable DV infrastructure to keep verification fast, automated, and production-grade. This role is hybrid, based out of Toronto, ON, Austin, TX or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in modern verification methodologies with strong SystemVerilog skills and exposure to structured testbench development. Comfortable working from block-level to system-level verification and reasoning about microarchitecture behavior from specs and waveforms. Proficient in Linux environments with Python, or Bash scripting for automate builds, parse logs, manage CI pipelines. Skilled in coverage-driven verification and confident debugging across RTL, testbench, and workload scenarios. Motivated by AI hardware and eager to learn verification strategies for new architectures and domains. What We Need Contribute to verification of Tensix IP and subsystems from early planning through tape-out, owning coverage goals and driving them to closure. Build and maintain reusable verification environments, agents, scoreboards, and supporting infrastructure in SystemVerilog and Python. Develop constrained-random and directed tests and close functional, code, and assertion coverage using data-driven approaches. Debug complex issues across RTL and testbench while collaborating with design, firmware, compiler, and architecture teams. Help evolve DV infrastructure including regression flows, CI/CD integration, EDA compute environments, and reproducible setups. Nice to have: Exposure to functional safety (FuSa) verification concepts for automotive AI workloads. Nice to have: Familiarity with formal verification methodologies, SVA (SystemVerilog Assertions), or formal property verification for complex control logic and microarchitectural corner cases. What You Will Learn How Tenstorrent verifies AI-native compute architectures including Tensix cores, RISC-V CPUs, matrix units, vector units, and datapath. How simulation, emulation, and software-driven workloads combine to validate both functional correctness and performance. How numerical precision formats such as BF16, FP4, and INT8 and on-chip dataflow impact verification complexity and coverage strategy. How to build scalable DV infrastructure across hybrid compute environments including containerized regression systems. How data analytics and modern AI tooling can enhance verification workflows and accelerate convergence. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification. This role is Remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Key Responsibilities: RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure. RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA. AI Assisted Design Adaption: To maximize the team’s output, the candidate actively uses AI tools to accelerate the CPU design process. Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team. Qualifications: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V. Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…) Deep understanding of CPU microarchitecture and PPA trade-off. Basic understanding of RISC-V Architecture including V-extension is preferred. Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL. Excellent problem-solving abilities and analytical skills. Strong communication skills, with the ability to convey complex technical concepts to diverse audiences. Ability to work collaboratively in a team-oriented environment and across multiple disciplines. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a high impact Emulation Engineer to help bring our SiP based AI or ML engines to life through scalable, high performance emulation platforms. This role is ideal for someone who thrives on technical ownership, solves system level problems, and wants to influence silicon debug, DV, and performance from the ground up. You will build the infrastructure that allows our chiplet based systems to be explored, tested, and validated across hardware, software, and architectural layers. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Bring 10+ years of SoC or ASIC experience, including a deep understanding of logic design, verification, and emulation platforms. Fluent in Verilog or SystemVerilog, C or C++, and SystemC, with hands-on experience using commercial emulators such as ZeBu, Palladium, or Veloce. Confident in architecting DV and emulation environments, from transactors to monitors to debug hooks, and automate everything you can. Collaborative and self driven, with a passion for mentoring junior engineers and working cross functionally with architecture, software, and DV teams. What We Need A passion to build and scale a multi chiplet emulation ecosystem that supports DV, software development, and power or performance debug. Comfort in developing testbenches, transactors, monitors, and support systems to enable high quality, high efficiency emulation usage. Experience in driving emulation coverage from functional and performance to low level software enablement, and automate as much of the flow as possible. To optimize the platform for frequency, resource sharing, and end user support, ensuring Tenstorrent teams get the most from emulation. What You Will Learn Building an emulation flow that supports chiplet based SiPs at scale, spanning AI workloads, interconnects, and system level power. How Tenstorrent integrates AI engines, RISC V CPUs, die to die links, PCIe, UCIe, and memory controllers into one unified platform. To align virtual prototyping, power analysis, and emulation into a full stack validation solution. How emulation sits at the core of a cross functional silicon bring up strategy, from RTL to post silicon debug and customer delivery. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a Verification Lead for our next-generation AI hardware. You’ll guide a top-tier team of Verification Engineers, shaping test strategies to validate functionality and performance of our AI core. This role requires expertise in AI-specific data types, common AI data-movement compute patterns, and on-chip network validation, combined with strong leadership and collaboration skills. This role is hybrid, based out Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A Seasoned Verification Leader: An experienced ASIC/SoC lead with proven track record of leading teams through complex tape-outs. An AI Hardware Specialist: An expert in the nuances of high-performance compute, specifically focused on AI/ML architectures and the intricacies of tensor-based operations. A Systems Architect at Heart: A strategist who views verification through a system-level lens, ensuring that hardware, software, and on-chip networks (NoC) harmonize perfectly. A Technical Mentor: A hands-on guide proficient in UVM, SystemVerilog, and cocotb, dedicated to elevating team capabilities and driving rigorous coverage-driven methodologies. What We Need Strategic AI Verification: Expertise in architecting verification plans for mixed-precision data types (FP8, BF16, INT8) and validating the accuracy of complex AI transformations. High-Performance NoC Expertise: Deep experience benchmarking on-chip networks under high-demand traffic, ensuring throughput, bandwidth, and congestion management meet peak requirements. Resiliency & Error Injection: A proactive approach to system stability, implementing robust concurrency controls and multi-core synchronization to handle edge-case failures. Platform-Agnostic Methodology: The ability to develop portable test strategies that scale seamlessly from subsystem-level simulations to FPGA and final Silicon. Cross-Functional Synergy: A collaborative mindset that bridges the gap between hardware architecture and software requirements to ensure performance targets are met. What You Will Learn Next-Gen AI/ML Tooling: Integrating your specific advanced automation frameworks and emerging AI-driven verification techniques into the existing lifecycle. Evolving Workload Dynamics: Gaining a deeper understanding of your proprietary AI workloads and how they stress memory access patterns uniquely within your architecture. Project-Specific Performance Bottlenecks: Identifying and mastering the unique architectural constraints of your specific SoC to push bandwidth limits further. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Graphcore

Verified

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root causes Degree in Computer Science, Engineering or related subject Ability to script in Python and/or TCL for automation and to solve design issues SystemVerilog Knowledge of digital design flows Desirable skills: Processor design Application specific blocks High-speed serial interfaces Complex third-party IP integration Arithmetic pipeline design Floating-point design Design for test Synthesis Timing Analysis Project Planning Power Integrity Silicon transistor Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Working within the Logical Design team, the Staff/Principal Silicon Logical Design Engineer is responsible for a wide range of logical design tasks which require working closely with other engineers within the Silicon department. This person is responsible for helping the team deliver high quality micro-architecture specifications and RTL for Graphcore chips, and assisting the rest of the Silicon teams to ensure we can meet the company objectives for silicon delivery. The Team The Logical Design team sits within the Silicon team. We are responsible for delivering the micro-architecture and RTL design to implement the chip architecture specification for Graphcore Silicon. Responsibilities and Duties Being part of the Logical Design team, producing high quality micro-architecture specification and RTL for Graphcore chips Ensuring good communication between different teams and across multiple sites Contributing to shared design infrastructure and flows Using EDA tools and the Graphcore design flow to design innovative technologies Contributing to block-level and chip-level checks and auditing (Linting, Synthesis, Timing Closure, CDC, RDC, Coverage) Working closely with Physical Design, Verification and DFT teams Essential skills: Degree in Computer Science, Engineering or a related subject Digital design experience in a relevant industry Be highly motivated, a self-starter, and a team player Ability to work across teams and finding solutions to problems Ability to solve design issues through programming, e.g. Python, Tcl Strong competency in SystemVerilog or VHDL Knowledge of digital design flows Capable of managing time and priorities Desirable: Processor design Application specific blocks High-speed serial interfaces Complex third-party IP integration Experience leading teams Arithmetic pipeline design Floating-point design Design for test Synthesis Timing Analysis Logical Equivalence Project Planning Power Integrity Silicon transistor knowledge Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

*]:pointer-events-auto R6Vx5W_threadScrollVars scroll-mb-[calc(var(--scroll-root-safe-area-inset-bottom,0px)+var(--thread-response-height))] scroll-mt-[calc(var(--header-height)+min(200px,max(70px,20svh)))]" data-turn-id="request-WEB:0fbc0e63-7a29-4549-b136-67f3c3174a55-0" data-turn-id-container="request-WEB:0fbc0e63-7a29-4549-b136-67f3c3174a55-0" data-testid="conversation-turn-2" data-turn="assistant"> About the job Own verification that turns complex silicon architecture into reliable AI compute hardware. As a Silicon Verification Engineer, you will help ensure Graphcore RTL matches the architecture specification. Your work will protect silicon quality before designs move into physical implementation. You will sit at the point where architecture, logical design and verification meet. That gives you direct influence over how issues are found, understood and resolved before they become costly. You will plan verification, define coverage, generate tests and diagnose failures. You will also improve shared infrastructure that helps engineers move faster and see problems earlier. The work is technically deep, but the impact is clear. You will help build the discipline, pace and quality needed for ambitious AI compute programs at scale. The team and culture The verification team works very closely with the Architecture, Logical Design and Physical Design teams. Work is shaped through clear plans, coverage goals, test results and direct technical feedback. You will be expected to take ownership, follow evidence and keep communication open across sites. The team values people who speak up early and make complex problems easier to solve. Decisions are made through technical reasoning, shared data and practical trade-offs. You will have room to lead from your expertise, not just your title. What we're looking for Verification experience in CPU, ASIC or closely related silicon environments Experience with UVM, SVA, assembly, compilers, Git or DRMS tools Ability to plan verification work and drive functional coverage to closure Strong debugging skills across RTL, software and shared verification infrastructure Confident in SystemVerilog and Python Benefits Flexible working: Balance your work and personal life with greater flexibility Generous leave: Take time to rest, recharge and enjoy life outside of work Retirement planning support: Up to 5% matched pension Phantom equity: Share in Graphcore’s success Workplace experience: Enjoy thoughtfully designed office spaces for collaboration, with free food and an on-site barista to support your day Peace of mind protection: Income protection and life assurance to provide financial security for you and your loved ones Flexible benefits: Tailor your benefits package with a choice of additional options, including private medical insurance and dental cover Optional benefits: Dental cover, health cash plan, private medical insurance, cycle to work scheme, give as you earn We welcome people from all backgrounds and experiences and are committed to building an inclusive environment where everyone can do their best work. We’re an equal opportunity employer and recognise that everyone brings different strengths and perspectives. If you need any adjustments during the interview process, just let us know - we’re happy to support you. Join the Team at Graphcore Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore brings together deep expertise to solve complex problems and deliver meaningful progress in AI compute. Ready to own verification work that directly shapes Graphcore silicon? Apply now to help build the future of AI compute.

Graphcore

Verified

About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. The Team The Verification team sits within the Silicon Design organisation. We ensure that the RTL delivered by Logical Design and used by Physical Design team implements Graphcore’s architectural needs and meets the company's quality standards. As a Director of Silicon Verification, you will help lead this multi-site organisation, define verification strategies across multiple silicon programs, and drive best in class execution to ensure high-quality, high-performance silicon delivery. Role Summary We are seeking a proven leader to help direct Graphcore’s verification strategy and methodologies. This role sets direction for the verification lifecycle including - planning, infrastructure, execution, coverage closure, debug strategy and sign-off for Graphcore’s complex, high performance AI accelerators. Reporting to the Senior Director of Verification the Director will partner closely with other teams such as Architecture, Logical Design, Physical Design, DFT, Systems as well as Program Management teams to ensure accurate implementation, accelerated debug cycles, high coverage confidence and predictable silicon delivery. Responsibilities Leadership & Strategy Define the long-term vision, roadmap and strategy for silicon functional verification across all Graphcore silicon programs. Build, lead, and develop a high performing, globally distributed verification organisation. Establish scalable methodologies, leading edge verification techniques, and best practice processes. Drive automation, tooling and infrastructure evolution to improve productivity and verification quality. Evaluate emerging tools and technologies and drive adoption to deliver competitive advantage. Technical Ownership Own verification planning, execution and sign off for all RTL blocks and top-level SoCs. Oversee definition of test plans including functional coverage targets. Drive close through prioritisation of test content and coverage signoff. Iterate plans to close verification gaps. Direct debugging strategies, triage processes and root-cause analysis workflows to enhance team productivity. Steer integration of verification technologies including formal methods, simulation acceleration/emulation and system level validation. Cross Functional Collaboration Ensure high quality feedback to other functions within the Silicon Team. Partner with Architecture to influence and refine specifications for verifiability and risk reduction. Collaborate with Logical Design to align on design intent, architectural corner cases and test scenarios. Work closely with Physical Design and DFT teams to ensure coherent verification of interfaces, timing assumptions and test structures. Lead post-silicon debug alignment where needed, ensuring learning cycles feed back into RTL and verification methodology. Execution & Delivery Deliver verification sign off on schedule across multiple parallel projects. Guide program risk management, resource planning, milestone creation, and verification budgeting. Drive consistent metrics-based verification management (structural and functional coverage, bug funnels, simulation performance, CI health, etc.). Provide scheduled reports into program management on progress with associated metrics based collaterol. Essential Skills Demonstrated ability to lead, scale and inspire high performing verification teams. Extensive verification leadership experience within CPU, GPU, ASIC or SoC environments. Deep understanding of modern verification methodologies, flows, and infrastructure. Strong capability in SystemVerilog, Python, C++ and Linux-based workflows. Expertise in diagnosing complex logic issues across RTL, testbench and system level domains. Strong communication, collaboration and stakeholder management skills across global sites. Desirable Skills UVM and advanced SystemVerilog Assertions (SVA). Experience with assembly languages and compiler toolchains (LLVM, GCC). Knowledge of DVCS tools (e.g., Git). Familiarity with distributed compute systems (SGE or other DRMS). Experience with XML, XPath/XSLT. Web technologies such as HTML/DOM, JavaScript, SQL. Exposure to emulation, FPGA prototyping, or formal verification tools. Benefits In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Graphcore

Verified

About Graphcore At Graphcore, we’re building the future of AI compute. We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale. As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world. We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary We are seeking a Director of Silicon Logical Design to lead and scale our Logical Design group within the Silicon department. This role is accountable for the overall strategy, technical direction, execution quality and team development for Graphcores microarchitecture and RTL design efforts. The Director will be responsible for ensuring that our logical design methodologies, architectures and RTL implementations meet world class standards for performance, power, area, and schedule. This leader will partner closely with Architecture, Physical Design, Verification, DFT and Program Management teams to ensure successful, predictable silicon delivery aligned with Graphcores long term product roadmap. The Team The Logical Design team deliver the micro-architecture and RTL that realise our advanced chip architectures. As Director, you will guide this multi site team, strengthen cross functional collaboration, and drive the evolution of our design flows and capabilities. Responsibilities and Duties Leadership & Strategy Define and execute the strategic roadmap for Logical Design, ensuring alignment with Graphcores silicon and product strategy. Lead, grow and mentor a high performing RTL/micro architecture design organisation. Establish and implement best in class design methodologies, documentation standards and quality metrics. Drive continuous improvement across team structure, workflows, tooling, and design processes. Technical Ownership Provide technical oversight of micro architecture specification and RTL development across all major blocks and subsystems. Guide architectural feasibility studies, contribute to architectural trade offs and micro architecture definition. Oversee the integration of third party IP, complex application specific blocks, and high performance custom designs. Ensure robust design sign off through high quality linting, synthesis, CDC/RDC, timing closure and coverage metrics. Cross-Functional Collaboration Partner closely with Physical Design, Verification, DFT, Architecture and Program Management teams to ensure cohesive planning and execution. Foster strong communication across teams and global sites, ensuring alignment on priorities, risks and deliverables. Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture. Execution & Delivery Own delivery of high quality, on schedule RTL for multiple parallel silicon programs. Establish scalable project planning and tracking practices, including resource planning and risk mitigation. Champion design automation and infrastructure improvements to accelerate productivity and improve design quality. Essential Skills & Experience Degree in Computer Science, Electrical Engineering or a related field; advanced degree preferred. Extensive experience in digital logical design, micro-architecture and RTL development for large scale, high performance silicon projects. Proven success leading and developing technical teams in a semiconductor environment. Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows. Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.). Demonstrated excellence in cross functional leadership and communication across global teams. Strong organisational skills with ability to manage multiple priorities and drive execution in fast-paced environments. Desirable Experience Processor or accelerator micro architecture. High-speed serial interfaces and complex, high bandwidth IP blocks. Arithmetic pipeline design and floating point datapaths. Advanced synthesis, timing analysis, power analysis, and logical equivalence checking. Design-for-test methodologies. Power integrity and silicon device level understanding. Experience with silicon bring-up and post-silicon validation. Program planning and multi-project execution leadership.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we are building open, state of art compute for AI and RISC‑V CPUs. You will lead the technical efforts and strategy around our existing emulation infrastructure for high‑performance CPUs that power these products. Your work will directly enable silicon bring‑up, validation, and customer‑ready systems. This role is hybrid, based out of Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have strong background in CPU verification, emulation, and debug. You are fluent in Verilog and SystemVerilog for complex SoC designs. You are a technical leader who drives complex debug efforts, solves ambiguous technical problems, and mentors younger engineers. Experience with Zebu emulation platforms is a significant plus. You collaborate closely with design, verification, and vendors to move fast and unblock teams. What We Need Lead the technical strategy and execution to scale and optimize existing emulation infrastructure on commercial and open‑source platforms. Enable the emulation infrastructure and workflow, including producing reliable emulation builds. Drive and lead complex cross-functional debug and root cause analysis efforts. Optimize emulation performance and regression flows with Design Verification teams and tool vendors. What You Will Learn How to bring state of art AI and CPU architectures to life on emulation. How to design large‑scale emulation regressions that mirror real customer workloads. How to tune emulation performance across different vendors and hardware platforms. How open hardware and software come together across Tenstorrent’s full compute stack. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Join the team building the silicon behind Tenstorrent’s custom AI platform. As an RTL Design Engineer, you will contribute to the development of next-generation AI hardware by implementing and optimizing micro-architectures, improving performance and power efficiency, and collaborating across hardware teams. This role offers the opportunity to work on challenging, high-impact designs in a fast-paced environment. This role hybrid, based out of Belgrade, Serbia. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are: An engineer with a strong foundation in digital design and micro-architecture. Familiar with RTL development, debugging, and performance analysis workflows, including clock/reset, power, boot, and debug logic. Comfortable writing Verilog or SystemVerilog and interpreting synthesis and timing results. Motivated to learn how high-performance AI hardware is built and optimized from the ground up. What We Need: Contributors who can implement and refine micro-architectural features for Tenstorrent’s AI hardware IP. Engineers who can analyze performance bottlenecks and suggest improvements that balance power, area, and frequency. Teammates who collaborate across RTL, DV, performance, and physical design to explore and evaluate design trade-offs. Developers who can debug RTL issues in both simulation and post-silicon environments and contribute to improving internal tools and flows. What You Will Learn: Techniques for developing high-performance RTL targeting AI and ML workloads. How power, performance, and area are balanced across design, verification, and physical implementation. Tools and methods used to evaluate design trade-offs and optimize compute architectures. What it takes to ship production-grade silicon that supports next-generation AI systems. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation. Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL. Skilled at using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation, debugging, and documentation analysis. Energetic about supporting diverse teams, from high-level software to low-level firmware, to solve complex runtime and build issues. What We Need Ability to integrate vendor and custom transactors into RTL testbenches while handling clock domain and tri-state resolution. Experience building Python APIs (using pybind11) and maintaining CMake-based compilation flows for emulation libraries. Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization (resets/clocking). A commitment to triaging and debugging the full stack, spanning from Python tests and C++ bindings down to hardware. What You Will Learn Deepening your expertise with world-class platforms like Synopsys Zebu for massive-scale silicon validation. Gaining a holistic view of chip development by bridging the gap between hardware RTL and software drivers. Building and optimizing large-scale emulation build and run tooling for high-performance engineering teams. Refining your ability to gather requirements and facilitate communication between hardware designers and software engineers. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPU chiplet with an emphasis on power analysis. The role involves defining CPUrail planning while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for Block rails, and managing the power vector plan for comprehensive coverage of Chip level. The position requires driving power analysis on RTL and Netlist using tools like Joules and PrimePower, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and workingwith post-silicon teams to correlate projections with silicon power measurements. This role is hybrid, based out of Tokyo, Japan We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Extensive experience in power analysis and optimization for complex ASICs (typically 10+ years of ASIC or related design experience). Comfortable working across RTL, synthesis, and physical design stages, including low‑power implementation techniques and ECO‑based timing closure. Proficient with power analysis tools (e.g., Joules, PrimePower) and scripting (Tcl plus at least one of Python or similar). Strong analytical and problem‑solving skills, with clear written and verbal communication when collaborating across SoC, board, and post‑silicon teams. Nice to have: familiarity with UPF/CPF low‑power intent, Verilog/SystemVerilog, CPU micro‑architecture and its power challenges, and basic thermal analysis. What We Need Own power analysis and projections for the CPU chiplet, with emphasis on defining and tracking power metrics throughout the design cycle. Define and maintain the power vector plan for comprehensive chiplet‑level and chip‑level coverage. Drive power analysis on RTL and netlist using tools such as Joules and PrimePower, partnering with RTL design, synthesis, and physical design teams to measure and optimize power. Evaluate and propose new power optimization techniques at RTL, synthesis, and physical design stages, and implement changes via timing ECO and flow updates. Tabulate and compare power metrics and reports across design iterations, and work with post‑silicon teams to correlate projections with silicon measurements. What You Will Learn How to define and execute a power strategy for a 2nm CPU chiplet within a multi‑chiplet system‑in‑package, including rail planning and system‑level PDN optimization. Best practices for end‑to‑end power closure, from RTL through netlist and physical design, in collaboration with global RTL, SoC, and board teams. How to correlate pre‑silicon power models with real silicon behavior and feed lessons learned back into next‑generation CPU and SiP architectures. How Tenstorrent integrates CPU chiplets, AI accelerators, and board‑level power delivery into a cohesive high‑performance platform. テンストレントジャパンについて 経済産業省を始めとする日本政府は予算、税制、政策のあらゆる面で世界と競争できるよう投資パッケージを準備しています。2024年にはテンストレントが持つ技術力、経験、人材が評価され、全国規模のプロジェクトを推進するための主要パートナーの 1 つに選ばれました。(詳細はこちらをご覧ください)　日本の半導体産業をより盛り上げるために様々な人材を募集しています。テンストレントジャパンや採用については人事担当（recruiting-jp@tenstorrent.com）までご連絡ください。 This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Engineer, SoC RTL Engineer We are looking for a Digital Design Engineer to help build and optimize high-performance chiplet-based SoC architectures. This role is ideal for passionate junior engineers or recent graduates who want to grow their career at the intersection of microarchitecture, RTL implementation, and performance/power-aware design. Location: Tokyo, Japan (Hybrid - Flexible working hours and remote work options available) We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Benefits & Work Style at Tokyo Office Competitive Salary: We offer a competitive compensation package aligned with industry standards, your baseline skills, and potential. Flexible Work Culture: To support a healthy work-life balance, we offer flexible working hours (flextime) and remote work options (hybrid style) based out of our Tokyo office. Who You Are An Aspiring Digital Design Engineer: You have a solid foundational understanding of computer architecture and digital logic design. Eager to Learn RTL: You have academic or internship experience in RTL development (SystemVerilog) and are excited to learn the full ASIC flow. PPA Conscious: You understand the basic concepts of optimizing for Power, Performance, and Area (PPA). Collaborative & Curious: You are a natural team player who thrives on learning from peers, participating in code reviews, and asking questions. Problem Solver: You possess strong analytical skills and a desire to tackle complex hardware design challenges. What You Will Do (What We Need) HDL Coding: Utilize hardware description languages (SystemVerilog) to implement and modify custom IP blocks and SoC components under the guidance of senior mentors. RTL Implementation: Assist in the design and integration of compute, interconnect, or memory-heavy blocks. Verification Support: Contribute to verification and validation efforts using emulation, FPGA prototyping, or basic UVM flows. Collaborate Across Teams: Work closely with senior engineers to understand design specifications and support backend synthesis and timing closure teams. Bonus Points: Basic understanding of RISC-V Architecture, on-chip fabric/interconnect designs, DFT, or basic hardware debugging experience is preferable but not required. What You Will Learn Advanced Chiplet Design: How cutting-edge chiplet designs are built, from initial spec to silicon. Industry-Leading Collaboration: What it takes to collaborate with global teams designing novel processor and memory architectures. Cross-Functional Workflows: How design, Design Verification (DV), physical design, and firmware teams come together to deliver world-class AI hardware. Mentorship: Receive hands-on guidance and mentorship from industry-leading silicon experts. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Sr. Design Verification Engineer to lead verification efforts on state of art digital designs. This role owns verification strategy, builds advanced test environments, mentors engineers, and ensures designs are fully tested for functionality, performance, and quality. You will help shape how we verify the compute engines that power the open future of AI and high performance compute. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Lead the definition and execution of comprehensive verification plans for complex digital blocks and systems. Drive verification methodologies and strategy across projects, setting best practices and standards. Build advanced test environments using SystemVerilog and UVM, and execute testbenches, cases, and coverage. Collaborate with architecture, design, and software teams to align on specifications and debug issues. Guide and mentor junior engineers, contributing to a high performing verification team. What We Need 10+ years of industry experience in digital design verification with a strong record of technical leadership. Deep expertise in SystemVerilog and UVM, along with familiarity with formal verification methods. Strong understanding of computer architecture, microarchitecture, and SoC integration. Hands-on experience with tools like Questa, VCS, or similar simulation environments. Excellent communication skills and the ability to lead cross functional collaboration. What You Will Learn Work at the intersection of next gen RISC V CPUs and AI accelerators in a chiplet based architecture. Influence verification strategy across multiple product lines in a rapidly evolving tech environment. Collaborate with top tier hardware architects and software teams building full stack solutions. Gain exposure to silicon bring up, post silicon validation, and end to end product delivery. Help shape industry leading verification methodologies in a fast paced, innovation first culture. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a CPU Verification Fellow to lead verification strategy and execution for next-generation RISC-V high-performance processors. This role requires deep CPU verification expertise, strong microarchitecture understanding, and the ability to guide large engineering teams from early design through tapeout and post-silicon validation. The ideal candidate has verified complex out-of-order, speculative, superscalar CPUs and can define scalable methodology across simulation, formal verification, emulation, FPGA, and silicon bring-up. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have deep experience verifying high-performance superscalar CPUs, ideally including out-of-order and speculative processors. You have strong knowledge of RISC-V architecture, including ISA compliance, privileged architecture, virtual memory, atomics, vector extensions, and memory model behavior. You are highly proficient in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, and advanced debug methodologies. You have hands-on experience with CPU reference models, instruction generators, ISS-based checking, or differential testing. You bring practical expertise with formal verification and large-scale CPU verification environments. What We Need A verification leader who can own strategy for RISC-V high-performance superscalar CPUs and CPU subsystems. An expert who can drive verification planning for out-of-order, speculative, superscalar microarchitectures. A technical leader who can build and scale test plans, coverage, checkers, assertions, scoreboards, and constrained-random environments. Someone who can verify key CPU features including frontend, branch prediction, rename, scheduling, execution, load-store, memory ordering, cache hierarchy, retirement, exceptions, interrupts, debug, and coherency interactions. A cross-functional partner who can work closely with architecture, RTL, performance modeling, SoC, firmware, compiler, and validation teams while mentoring senior engineers and establishing best practices across the CPU verification organization. What You Will Learn How Tenstorrent develops next-generation RISC-V high-performance superscalar processors from early design through tapeout and post-silicon validation. How CPU verification strategy scales across simulation, formal verification, emulation, FPGA prototyping, and silicon bring-up. How advanced CPU features such as coherency, virtual memory, atomics, vector extensions, and custom extensions are verified in complex real-world systems. How to drive verification closure, bug triage, root-cause analysis, coverage closure, and tapeout readiness at the highest levels of technical leadership. How Tenstorrent teams collaborate across architecture, design, firmware, compiler, and validation to build cutting-edge compute products. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Qualcomm

Verified

Join Qualcomm Snapdragon Modem verification team. Construct constrained-random UVM testbenches, write functional coverage groups, and execute gate-level simulation regression runs.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Staff Design for Test STA Engineer at Tenstorrent, you will be a key technical leader in ensuring the testability, quality, and performance of our next-generation AI processors. This role requires a good understanding of both Design for Test (DFT) architecture and implementation, as well as comprehensive expertise in Static Timing Analysis (STA) for complex SoCs. You will be responsible for defining and implementing the full DFT methodology for our high-speed, multi-core designs, owning the top-level timing constraints and sign-off for all DFT modes, and collaborating closely with RTL, Physical Design, and Product Engineering teams to achieve first-pass silicon success. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deep knowledge of core DFT concepts including Scan Compression and insertion, Memory BIST and repair schemes, JTAG/IJTAG, and at-speed test methodologies. Comprehensive understanding of Clock Domain Crossings (CDC), Reset Domain Crossings (RDC), timing sign-off modes and constraints, and proficiency in using industry-leading Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Tempus etc). Deep knowledge of DFT specific timing modes including JTAG, Scan Shift, Scan Slow Capture, Scan Fast Capture, Memory BIST etc. Experience in Verilog/SystemVerilog RTL coding and back-annotated gate-level verification. What We Need Coordinate DFT requirements across SOC, IP and product teams and work closely with multi-functional teams to support DFT RTL level insertion, synthesis and scan insertion, place-and-route, and static-timing-analysis and timing closure. Lead the definition, generation, and validation of comprehensive DFT timing constraints (SDC) to ensure timing closure for all test modes (e.g., Scan, JTAG, Memory BIST). Own the STA sign-off for DFT modes at both the block and top-level, including corners and operating conditions, using industry-standard tools (e.g., PrimeTime, Tempus etc). Work closely with the Physical Design team (Synthesis, P&R) to drive timing convergence, resolve complex timing violations, and generate necessary timing ECOs. Identify and implement improvements to existing DFT and STA flows, enhancing efficiency and robustness. Participate in ATE targeted test patterns, validation and silicon- debug Work closely with test and product engineering teams on silicon characterization and validation. What You Will Learn Advanced Design for Test (DFT) methodologies for cutting-edge AI processor architectures, including comprehensive scan insertion, Memory BIST, and at-speed test strategies In-depth Static Timing Analysis (STA) techniques for complex multi-core SoCs, mastering industry-standard tools like PrimeTime and Tempus to ensure timing closure across diverse operational modes Sophisticated cross-functional collaboration skills, working seamlessly with RTL, Physical Design, and Product Engineering teams to drive first-pass silicon success Innovative problem-solving approaches for resolving complex timing violations and optimizing test flows in high-performance semiconductor design environments Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid , based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with protocols such as AXI, ACE, CHI, or PCIe. Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements. What You Will Learn Verification of advanced CPU and memory-management related IPs used in AI/ML systems. Building scalable UVM environments and improving verification methodologies. Collaborating across architecture, RTL, and validation teams throughout the development cycle. Using Automation and AI-assisted tools to improve productivity and debug efficiency Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 3–6 years of experience in ASIC design, with expertise in microarchitecture and RTL for complex subsystems. Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes. Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI). Awareness of functional safety (ISO 26262) practices in hardware design. What We Need Ability to own microarchitecture definition and RTL development of Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller. Experience driving verification closure, performance debug, synthesis, timing, and power optimization. Strong skills in LINT, CDC/RDC, and power intent checks. Proficiency with DV and analysis tools like Verdi, NCSIM, and power estimation tools. Hands-on experience in design-for-power, debug, and test methodologies. What You Will Learn Building power-efficient, high-performance subsystems for advanced RISC-V/ARM architectures. Cross-functional collaboration from concept to silicon bring-up. Enhancing subsystem performance through innovative power, performance, and area optimizations. Leadership and mentorship experience by guiding junior design engineers. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Graphcore

Verified

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 4-8 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root causes Degree in Computer Science, Engineering or related subject Ability to script in Python and/or TCL for automation and to solve design issues SystemVerilog Knowledge of digital design flows Desirable skills: Processor design Application specific blocks High-speed serial interfaces Complex third-party IP integration Arithmetic pipeline design Floating-point design Design for test Synthesis Timing Analysis Project Planning Power Integrity Silicon transistor Benefits: In addition to a competitive salary, Graphcore offers a competitive benefits package. We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions. The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Implementation of DFT features into RTL using verilog. Understanding of DFT Architectures and micro-architectures. ATPG and test coverage analysis using industry standard tools. JTAG, Scan Compression, and ASST implementation. Gate level simulation using Synopsys VCS and Verdi. Support silicon bring-up and debug. MBIST planning, implementation, and verification. Support Test Engineering on planning, patterns, and debug. Develop efficient DFx flows and methodology compatible with front end and physical design flows Experience & Qualifications: BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques. DFx experience implementing in finFET technologies. Experience with industry standard ATPG and DFx insertion CAD tools. Familiarity with SystemVerilog and UVM. Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors. Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling. Good understanding of high-performance, low-power design fundamentals. Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. Exposure to post-silicon testing and tester pattern debug are major assets. Experience with Fault Campaigns a plus. Strong problem solving and debug skills across various levels of design hierarchies. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The SoC Chiplet Design Lead will drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC and automotive markets that push the boundaries of performance, scalability, and efficiency. You’ll lead cross-functional teams through the entire SoC lifecycle—from concept and architecture through RTL, verification, and tape-out—while ensuring design excellence and integration success. This role is hybrid, based out of Toronto, Ottawa, Boston, Austin, or Santa Clara, with potential for remote work within North America on a case-by-case basis. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deep background in SoC and chiplet design, with expertise in RTL design (Verilog/SystemVerilog) and digital architecture. Experienced in cross-functional collaboration, partnering with system, verification, physical design and packaging teams to deliver complex silicon. Skilled at balancing tradeoffs across performance, power, cost, and features. A strong technical leader and mentor, with a passion for developing high-performing engineering teams. What We Need Proven experience leading end-to-end SoC development, from concept to volume production. Mastery of SoC verification, synthesis, and timing closure workflows. Ability to manage internal and third-party IP integrations, lead design reviews, and closely collaborate with the DFT team Strategic mindset to align technical goals with product timelines and quality targets. What You Will Learn Building next-generation SoC chiplet architectures at advanced process nodes (e.g., 7nm, 5nm). Applying cutting-edge low-power and high-speed design (RISCV, UCIe, coherent fabrics, etc.). Enhancing cross-domain collaboration between hardware, software, and packaging disciplines. Shaping best practices and tools for scalable, efficient SoC design and validation. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.